In order to meet demands for increasing the speed and capacity of data transmission among a plurality of semiconductor chips and for reducing the packaging area of a semiconductor device, a variety of semiconductor devices wherein a plurality of semiconductor chips are stacked have been realized. Of these semiconductor devices, there is known a semiconductor device having a configuration in which electrodes formed on a chip are closely arranged contactlessly and oppositely to each other and inter-chip signal transmission is performed by means of capacitive coupling between the two electrodes. In this configuration, contact failure that often occurs when electrodes are brought into contact with each other, presents no problem. For this reason, this configuration is expected to come into practical use for the connection between semiconductor chips that requires multitude of electrodes, particularly among a plurality of CPUs, between a CPU and a memory, and among a plurality of memories, and for a semiconductor device in which these semiconductor chips are stacked.
FIG. 1 illustrates a typical semiconductor device for performing contactless signal transmission, wherein electrode A and electrode B are formed on the circuit surfaces of chip A and chip B, respectively, adjacently oppositely to each other. When electrode A is assumed to be a driver and electrode B is assumed to be a receiver, then electrostatic capacitance is present between the two electrodes, causing the two electrodes to capacitively couple with each other. That is, electrical lines of force generated from electrode A at this time reach electrode B, thereby placing the two electrodes in a state of being electrically coupled with each other (capacitive coupling). Consequently, a signal exchange is made from electrode A to electrode B.
In this related art, however, signal transmission among three or more chips is not possible, though signal transmission between opposed chips, i.e., one-to-one inter-chip transmission, is possible. When a signal is transmitted from lowermost-layer chip A to uppermost-layer chip C in cases where conventional chips are simply stacked in a three-dimensional manner as illustrated in FIG. 2, assuming, for example, that the chips are configured using a commonly-used semiconductor substrate (for example, a silicon substrate), then electric fields transmitted from the lowermost layer to the uppermost layer attenuate due to the effect of conductive property (loss) that the substrate of chip B located in an intermediate layer has. Therefore, it has been difficult to adequately perform signal transmission between chip A and chip C.
Hence, in order to enable a signal transmission among three or more chips, Patent documents 1 and 2 disclose a stacked electrical circuit in which a conductive region for penetrating through the front and back sides of a silicon substrate is provided and a signal transmission is performed with the mode thereof categorized into (1) a case where a signal from a wafer stacked on an upper side is received; (2) a case where a signal is transmitted to a wafer stacked on an upper side; (3) a case where a signal from a wafer stacked on a lower side is received; and (4) a case where a signal is transmitted to a wafer stacked on a lower side.
In addition, Patent document 3 discloses a three-layer modular electronic system, though the system is intended not for signal transmission among three or more chips but for signal transmission between two chips. In the system, electrodes are provided on upper and lower sides between the chips and a dielectric material substrate, in which an interconnection that penetrates the electrodes is formed, is sandwiched between the electrodes.    Patent document 1: Japanese Patent Laid-Open No. 56-002662    Patent document 2: Japanese Patent Laid-Open No. 62-020362    Patent document 3: Published Japanese translations of PCT international publication No. 09-504908